In some electronic systems, signaling between electrical components flows through wires, sometimes referred to as traces, conductors, or electrical paths, on or within printed circuit boards (PCBs), integrated circuits (ICs), or other structures of the electronic system. Conventionally, a signal is carried over a single wire or, for a differential signal, a pair of wires.
Recently, multi-wire signaling schemes (i.e., signaling over more than two wires) have been proposed. For example, C-PHY is a mobile device communication interface for the Mobile Industry Processor Interface (MIPI) Alliance Specification. C-PHY uses a three phase channel (referred to as a “trio”) to transmit data. That is, in contrast with conventional physical interfaces (PHYs) that use a single wire or a differential wire pair for a given channel, a C-PHY channel employs three wires (also referred to as “lanes”). For a given data transmission (e.g., of a bit or symbol), two of the wires are used (active) while the third wire is in a high impedance state (e.g., floating). Over a series of data transmissions, different pairs of the three wires are used to transmit the data.
Multi-wire signaling may be subject to signal transmission issues such as jitter. Jitter is the undesired deviation from true periodicity of an assumed periodic signal in data transmission. For example, over a series of symbol transmissions, there may be timing skew between the symbols when they are received at a receiver. This skew manifests itself as jitter. In view of the above, a need exists for improved circuit techniques for addressing jitter or other similar transmission issues in wire-based signaling.